1. Field of the Invention
The present invention relates to power-saving techniques in computer systems. More specifically, the present invention relates to a method and apparatus for changing the clock frequency of a memory subsystem for power-saving purposes.
2. Related Art
Modem computing systems are growing increasingly more capable because integrated circuit (IC) chips within these computer systems are operating at increasingly faster clock speeds. At the same time, these IC chips also consume more power due to these faster clock speeds. However, in many computing environments, it is desirable to reduce power consumption, for example, in mobile computing systems.
One common technique to save power is to dynamically manage system power consumption through clock-frequency scaling. For example, the clock frequency for an IC chip may be reduced during periods of operation when workload is light, thereby reducing power-consumption. Reducing the clock frequency in this way also allows the operating voltage to be reduced, thereby enabling even more power savings. Note that when the workload increases again, the clock frequency and voltage can be restored to their previous levels.
A memory subsystem within a computer system consumes a significant amount of power. Hence, providing power savings in a memory subsystem through dynamic clock-frequency scaling is not uncommon. Memory subsystems are commonly designed around double-data-rate (DDR) memory chips, which have become the dominant memory system technology. Such memory subsystems allow the DDR chips to change to a new clock frequency when the chips are in a standard self-refresh mode. More specifically, performing the clock frequency change during the self-refresh mode involves: pausing or discarding all outstanding memory subsystem operations; changing the clock frequency to a new value; and resuming or repeating the memory operations when the new value is reached.
Unfortunately, suspending memory operations for a long period of time during clock frequency changes is not desirable for many user applications, in particular during real-time applications such as audio and video playback. Hence, it is desirable to change the clock frequency as quickly as possible to minimize the unusable time. However, other system components sharing the same clock source may malfunction during an abrupt change in the clock frequency.
To deal with this problem, the clock frequency can be gradually changed through a “slew” operation using a phase-lock loop (PLL), which allows the clock frequency to ramp up or down slowly and continuously with tolerable phase noise. Unfortunately, such a frequency-slew operation may conflict with the effective phase-tracking range of downstream delay-locked loops (DLLs), which are typically found in the DDR memory chips. Commonly, DLLs are used in DDR chips to reduce clock skew in different parts of the memory and to synchronize data output timing with the input clock. Generally, DLLs in DDR chips can dynamically track small phase changes induced by clock frequency shifts and can realign to the clock. However, when the cumulative frequency change becomes larger than the DLL's tracking ranging, the DLL tracking will fail, which will necessitate a reset of the DLL, so that the DLL can relock to the clock. As a result, the frequency-slew operation will have to be halted.
Hence, there is a need for a clock-frequency changing technique which can simultaneously accommodate requirements for the PLL, the DLL, memory components, and user applications during a clock frequency change.